1. Field of the Invention
The present invention relates to a semiconductor storage apparatus and in particular, to a layout of MOS transistors which constitute a sense amplifier activation signal generating circuit.
2. Description of the Prior Art
In recent years, low-resistance metal lines disposed on multiple layers are used in semiconductor storage apparatuses. For example, in highly integrated DRAMs such as 16-M DRAMs or DRAMs of the following generations, low resistance metal lines such as aluminum lines and high-melting-point metal lines are disposed on two layers. Thus, the layout of an array area consisting of memory cells, sense amplifiers, a row decoder, a column decoder, and so forth has been improved. A first conventional layout is shown in FIG. 4.
In FIG. 4, memory cell areas 55 and sense amplifier areas 56 are alternately disposed as a major portion of array area 57. In each memory cell area 55, memory cells are disposed. In each sense amplifier area 57, sense amplifiers SA are disposed. Column decoder 51 is disposed at an edge portion of the array area 57. Column selection signals 52 that are outputted from column decoder 51 are disposed in array area 57 with metal lines disposed on a second layer (upper layer). Each of column selection signals 52 is connected to switching transistors I/O SWs of each sense amplifiers SA.
Sense amplifier activation signal generating circuits 53 are disposed in peripheral circuit area 58 that is disposed outside array area 57. Sense amplifier activation signals SAP and SAN that are output signals of each of sense amplifier activation signal generating circuits 53 are disposed in sense amplifier area 56 with metal lines disposed on a first layer (lower layer).
In the case that a semiconductor storage apparatus is laid out with two layers of low resistance metal lines, the thickness of the lower metal wring layer for the sense amplifier activation signals SAP and SAN should be decreased in order to flatten a base insulation film of metal lines for column selection signals 52 disposed on the upper layer. For example, when the film thickness of the upper metal lines is 1 .mu.m, the film thickness of the lower metal lines should be around 0.5 .mu.m. Thus, the stray resistance of the lower metal lines increases.
The sense amplifier activation signals SAP and SAN are connected to many sense amplifiers SA (around 1024 sense amplifiers SA for a 16-M DRAM). When a sense amplifier is operated, a large current flows. Thus, when the stray resistance increases, the charging/discharging capacity of the sense amplifiers SA degrades, whereby the high speed operation and stable operation of the sense amplifiers SA are adversely affected.
In order to solve such a problem, the width of lines for sense amplifier activation signals SAP and SAN is increased. In this case, the size of the sense amplifier becomes large and thus the size of the semiconductor chip becomes large. In the latest DRAM (for example, a 64-M DRAM), around 34 sense amplifier areas 56 are disposed in a row. Thus, the increased size of one sense amplifier is multiplied by 34 times for the size of a semiconductor chip.
In another conventional layout, a sense amplifier activation signal generating circuit is divided into a plurality of portions and disposed in the vicinity of sense amplifiers. Thus, the number of sense amplifiers connected to each sense amplifier activation signal is decreased so that the amount of charging/discharging current is decreased. In addition, the length of lines is decreased so as to decrease the stray resistance of the lines.
FIG. 5 is a schematic diagram showing a second conventional layout in which a sense amplifier activation signal generating circuit is disposed in a sense amplifier area (for example, ESSCC PROCEEDINGS, PP. 41-44, 1993).
In FIG. 5, MOS transistors 31 and 32 which constitute a sense amplifier activation signal generating circuit are provided for four sense amplifiers SA and disposed adjacent to four sense amplifiers SA. The sources of MOS transistors 31 and 32 are connected to metal lines 39a and 39b that are a ground line and a power line disposed on the upper layer, respectively. Metal lines 39a and 39b are alternately disposed among column selection signals 39c to 39f in parallel.
In such a layout, since MOS transistors 31 and 32 of the sense amplifier activation signal generating circuit activate only four sense amplifiers SA, the width of lines connected to the sense amplifiers SA can be decreased. In addition, since the sources of MOS transistors 31 and 32 are connected to metal lines on the thick upper layer in a short distance, the charging/discharging capacity can be increased.
However, when such a layout is used, since MOS transistors 31 and 32 that generate sense amplifier activation signals should be added, the area of sense amplifier area 33 is increased.
Estimating the increase for a 64-M DRAM, the size of each sense amplifier is increased by 7 .mu.m. Thus, the size of the longer side of the semiconductor chip is increased by a total of 238 .mu.m.
In order to prevent the increase of the size of each sense amplifier, a third conventional layout has been proposed. In the third layout, a sense amplifier activation signal generating circuit is disposed in a position different from the position in the first solution.
In recent years, in order to decrease the resistance of word lines, DRAMS have low resistance metal lines disposed in parallel with the word lines and connected at predetermined intervals, for example every 32 sense amplifiers, with the word lines in a memory cell area. Thus, since the connection area has a certain opening, the sense amplifier area also has a certain opening.
In a highly integrated storage apparatus such as 64-M DRAMs or DRAMs of the following generations, a word line is hierarchically selected. A word line selecting circuit is disposed at a connected portion of a word line with a metal line. In this case, there is an opening between adjacent sense amplifier areas. In addition, the opening is larger than the mere connected portion which was explained above.
In the third conventional layout, a sense amplifier activation signal generating circuit is disposed in the opening in the sense amplifier areas.
FIG. 6 is a schematic diagram showing the structure of such a DRAM.
In FIG. 6, in order to decrease the resistance of lead lines, MOS transistors 41 and 42 that constitute a sense amplifier activation signal generating circuit are disposed in a connected area of a word line with a low resistance metal line or an opening area 48 which is between sense amplifiers SA and is adjacent to areas 46 of a word line selecting circuit. The sources of MOS transistors 41 and 42 are connected to ground line 49b and power line 49a, respectively. Ground line 49a and power line 49b are disposed in parallel with column selection signals 49c to 49f and in opening 48 between sense amplifier area 43.
However, in this case, power line 49b and ground line 49a cannot be disposed with a sufficient width. In other words, when opening area 48 is disposed adjacent to the connected portion of the word line and the low resistance metal line, the width of opening area 48 is as small as several .mu.m. On the other hand, when opening area 48 is disposed adjacent to word line selecting circuits 46, the width of opening area 48 is around 20 to 30 .mu.m. However, since a signal line for selecting a word line is also disposed, the area remained for power line 49b and ground line 49a becomes small.
A fourth conventional layout in which a power line and a ground line are alternately disposed between column selection signal lines, which is similar to the first solution shown in FIG. 5, has been proposed (for example, ISSCC, pp. 108-109, Feb. 1991).
FIG. 7 is a schematic diagram showing the structure of such DRAM. In FIG. 7, ground line 49a and power line 49b disposed among column selection signal lines 49c to 49f are connected to MOS transistors 41 and 42 via a ground line 44c and a power line 45c disposed in sense amplifier area 43, respectively.
However, in this solution, since power line 45c and ground line 44c are disposed in sense amplifier area 43, the size of the sense amplifier is increased. In addition, since metal lines of sense amplifier area 43 are disposed on the lower layer, the thickness of the lower layer should be decreased. If the thickness is decreased, the stray resistance increases. On the other hand, when the width of the lines is increased in order to decrease the stray resistance, the size of the sense amplifier is further increased.